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PRELIMINARY
MX27C1610
16M-BIT [2M x 8/1M x 16] CMOS OTP ROM
FEATURES
* * * * * 2M x 8 or 1M x 16 organization 5V Vcc for Read operation 10V Vpp Programming operation Fast access time: 100/120 ns Totally static operation * * * * Completely TTL compatible Operating current: 60mA Standby current: 100uA Package type: - 42 pin plastic DIP
GENERAL DESCRIPTION
The MX27C1610 is a 16M-bit, One Time Programmable Read Only Memory. It is organized as 2M x 8 or 1M x 16 and has a static standby mode, and features fast programming. For programming outside from the system, existing EPROM programmers may be used. The MX27C1610 supports a intelligent fast programming algorithm which can result in programming time of less than two minutes. This One Time Programmable Read Only Memory is packaged in industry standard 42 pin dual-in-line plastic package.
PIN CONFIGURATIONS
PDIP
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
PIN DESCRIPTION
SYMBOL A0~A19 Q0~Q14 CE OE BYTE/VPP Q15/A-1 VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Word/Byte Selection /Program Supply Voltage Q15(Word mode)/LSB addr. (Byte mode) Power Supply Pin (+5V) Ground Pin
MX27C1610
BLOCK DIAGRAM
CE OE BYTE/VPP CONTROL LOGIC OUTPUT BUFFERS Q0~Q14 Q15/A-1
A0~A19 ADDRESS INPUTS
. . . . . . . .
Y-DECODER
. . . . . . . .
Y-DECODER
X-DECODER
16M BIT CELL MAXTRIX
VCC VSS
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TRUTH TABLE OF BYTE FUNCTION
BYTE MODE(BYTE = GND) CE H L L OE X H L Q15/A-1 X X A-1 input MODE Non selected Non selected Selected Q0-Q7 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
WORD MODE(BYTE = VCC) CE H L L OE X H L Q15/A-1 High Z High Z DOUT MODE Non selected Non selected Selected Q0-Q7 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
NOTE : X = H or L
FUNCTIONAL DESCRIPTION
READ MODE The MX27C1610 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE's, assuming that CE has been LOW and addresses have been stable for at least tACC - t OE. WORD-WIDE MODE With BYTE/VPP at VCC 0.2V outputs Q0-7 present data Q0-7 and outputs Q8-15 present data Q8-15, after CE and OE are appropriately enabled. BYTE-WIDE MODE With BYTE/VPP at GND 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits Q0-7.
STANDBY MODE The MX27C1610 has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC 0.2V. The MX27C1610 also has a TTL-standby mode which reduces the maximum VCC current to 4 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
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SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on One Time Programmable Read Only Memory arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. WRITE OPERATIONS Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID and Program command. In the event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program cycle, the CIR informs the write state machine, and the write state machine and the write state machine will control the program sequences and the CIR will only respond to status reads. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. See command definition table below.
MODE SELECT TABLE
BYTE/ MODE Read (Word) (2) Read (Upper Byte) (2) Read (Lower Byte) (2) Output Disable (2) Standby (2) Write Operation (2) ManufacturerID(3)(1) Device ID(3)(1) CE VIL VIL VIL VIL VIH VIL VIL VIL OE VIL VIL VIL VIH X VIH VIL VIL A9 X X X X X X VH VH A0 X X X X X X VIL VIH Q15/A-1 Q15 Out VIH VIL High Z High Z Q15 In 0B 0B VPP(5) VIH VIL VIL X X VPP VIH VIH Q8-14 Q8-14 Out High Z High Z High Z High Z Q8-14 In 00H 00H Q0-7 Q0-7 Out Q8-15 Out Q0-7 Out High Z High Z Q0-7 In C2H 6AH
NOTES: 1. VH = 10V 0.5V 2. X Either VIL or VIH. 3. A1= VIL, other address lines not specified are at "X" states 4. See DC Programming Characteristics for VPP voltages. 5. BYTE/VPP is intended for operation under DC Voltage conditions only. VPP=10V 0.5V for write operation
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COMMAND DEFINITIONS OF WRITE OPERATION TABLE
Command Sequence Bus Write Cycles Req'd First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Addr Data Addr Data Addr Data
Read/ Reset 4
Silicon ID Read 4
Page/Byte Program 4
Read Status Reg. 4
Clear Status Reg. 3
5555H AAH 2AAAH 55H 5555H F0H RA RD
5555H AAH 2AAAH 55H 5555H 90H 00H/01H C2H/6AH
5555H AAH 2AAAH 55H 5555H A0H PA PD
5555H AAH 2AAAH 55H 5555H 70H X SRD
5555H AAH 2AAAH 55H 5555H 50H
Fourth Bus Addr Read/Write Cycle Data
NOTES: 1. In the write operation mode, BYTE/VPP should be set to 10V0.5V. 2. 5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14. 3. RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. PO=Data to be programmed at location PA.
DEVICE OPERATION
SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (10Vo.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0 and A1. The manufacturer and device codes may also be read via the command register, for instances when the MX27C1610 is programmed in a system without access to high voltage on the A9 pin.
MX27C1610 Silion ID Codes
Type Manufacturer Code** Device Code** A19 X X A18 A17 X X X X A16 X X A1 VIL VIL A0 Code(HEX) DQ7 DQ6 VIL VIH C2H* 6AH* 1 0 1 1 DQ5 DQ4 DQ3 DQ2 0 1 0 0 0 1 0 0 DQ1 DQ0 1 1 0 0
* The high byte of the code will be 00H and low byte of the code will be C2H for Manufacturer code and 6AH of Device code. ** All other address lines not specified are also at "X" state. X=VIH or VIL.
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READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX27C1610 is accessed when CE and OE are low the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. Note that the read/reset command is not valid when program is in progress.
WORD-WIDE LOAD
Word loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. A word load is performed by applying a low pulse on the CE input with CE and OE high. The address is latched on the falling edge of CE. The data is latched by the rising edge of CE.
PROGRAM
The device is programmed on a page basis. Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data word has been loaded into the device, successive words are entered in the same manner. The time between word loads must be less than 30us otherwise the load period could be teminated. A6 to A19 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of CE. A0 to A5 specify the word address withih the page. The word may be loaded in any order; sequential loading is not required. If a high to low transition of CE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on Q7 is "1" at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.
PAGE PROGRAM
The device is set up in the programming mode when the programming Voltage Vpp=10V is applied with Vcc=5V, and OE=VIH. Any attempt to write to the device without the threecycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command (see command table) sequence is given, a word load is performed by applying a low pulse on the CE input with CE low and OE high. The address is latched on the falling edge of CE The data is latched by the rising edge of CE . Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below.
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READ STATUS REGISTER
The MXIC's16 Mbit OTP ROM contains a status register which may be read to determine when a program operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM can set status bit4 and bit7. However, the WSM can only clear bit 7 but can not clear bit 4. If Program fail status bit is detected, the Status Register is not cleared until the "Clear Status Register command" is issued. The MX27C1610 automatically outputs Status Register data when read after Page Program or Read Status Command write cycle. The internal state machine is set for reading array data upon device power-up.
CLEAR STATUS REGISTER
The Program fail status bit (Q4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table below). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages . The status register may then be read to determine if an error occurred during that programming series. This adds flexibility to the way the device may be programmed. Additionally, once the program fail bit happens, the program operation can not be performed further. The program fail bit must be reset by system software before further page program are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID.
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STATUS REGISTER TABLE
STATUS IN PROGRESS PROGRAM COMPLETE PROGRAM FAIL PROGRAM AFTER CLEARING STATUS REGISTER NOTES 1,2 1,2 1,3 Q7 0 1 1 1 Q4 0 0 1 0 Q3 0 0 0 0
NOTES: 1. Q7 : WRITE STATE MACHINE STATUS 1 = READY, 0 = BUSY Q4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM Q3=0 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register. 2. PROGRAM STATUS is for the status during Page Programming. 3. FAIL STATUS bit(Q4) is provied during Page Program mode.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the command register is disabled and all internal program circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 BYTE/VPP VALUE 0C to 70 C -65C to 125C -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V -0.5V to 12.0V
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE = VIH. To initiate a write cycle CE must be a logical zero while OE is a logical one, and BYTE/VPP=10V.
NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
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CAPACITANCE TA = 25 f = 1.0 MHz C,
SYMBOL CIN CVPP COUT PARAMETER Input Capacitance VPP Capacitance Output Capacitance MIN. TYP. MAX. 14 20 16 UNIT pF pF pF CONDITIONS VIN = 0V VPP=0V VOUT = 0V
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.6K ohm +5V
CL 1.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V TEST POINTS 0.8V
0.45V
2.0V 0.8V OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns.
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DC CHARACTERISTICS TA = 0 to 70 VCC = 5V10% C C,
SYMBOL ILI ILO ISB1 ISB2 ICC1 PARAMETER Input Leakage Current Output Leakage Current VCC Standby Current(CMOS) VCC Standby Current(TTL) VCC Read Current 1 50 60 mA 2 4 mA 1 1 100 uA 1 10 uA NOTES 1 MIN. TYP. MAX. 10 UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE = VCC0.2V VCC = VCC Max CE = VIH VCC = VCC Max CMOS: CE = GND 0.2V BYTE/VPP = GND0.2V or VCC 0.2V Inputs = GND0.2V or VCC 0.2V TTL : CE = VIL, BYTE/VPP = VIL or VIH Inputs = VIL or VIH, f = 10MHz, IOUT = 0 mA ICC2 VCC Read Current 1 30 35 mA VCC = VCC Max, CMOS: CE = GND 0.2V BYTE/VPP = VCC0.2V or GND 0.2V Inputs = GND0.2V or VCC0.2V TTL: CE= VIL, BYTE/VPP = VIH or VIL Inputs = VIL or VIH, f = 5MHz, IOUT = 0mA ICC4 VIL VIH VOL VOH VCC Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 2 3 -0.3 2.4 0.8 0.45 V V V IOL = 2.1mA IOH = -2mA VCC+0.3 V 1 30 50 mA Program in Progress
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25C. These currents are valid for all product versions (package and speeds). 2. VIL min. = -1.0V for pulse width 50ns. VIL min. = -2.0V for pulse width 20ns. 3. VIH max. = VCC + 1.5V for pulse width 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.
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AC CHARACTERISTICS --- READ OPERATIONS
SYMBOL tACC tCE tOE tDF tOH tBACC tBHZ 27C1610-10 DESCRIPTIONS MIN. MAX. Address to Output Delay 100 CE to Output Delay 100 OE to Output Delay 50 OE High to Output in High Z 0 35 Address to Output hold 0 BYTE/VPP to Output Delay 100 BYTE/VPP Low to Output in High Z 50 27C1610-12 MIN. MAX. 120 120 50 0 35 0 120 50 UNIT ns ns ns ns ns ns ns CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL CE= OE=VIL CE=VIL
NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
TEST CONDITIONS:
* * * * Input pulse levels: 0.45V/2.4V Input rise and fall times: 10ns Output load: 1TTL gate+100pF(Including scope and jig) Reference levels for measuring timing: 0.8V, 2.0V
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Figure 1. READ TIMING WAVEFORMS
Vcc Power-up
VIH
Standby
Device and address selection
Outputs Enabled Data valid
Standby
Vcc Power-down
ADDRESSES
VIL
ADDRESSES STABLE
VIH
CE
VIL
VIH VIL tOE tCE tOH VOH tDF
OE
DATA OUT
VOL
HIGH Z
Data out valid
HIGH Z
tACC
5.0V
VCC
GND
NOTE: 1.For real world application, BYTE/VPP pin should be either static high(word mode) or static low(byte mode); dynamic switching of BYTE/VPP pin is not recommended.
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Figure 2. BYTE/VPP TIMING WAVEFORMS
VIH
ADDRESSES
VIL
ADDRESSES STABLE
VIH VIL
CE
VIH VIL tDF tBACC VIH tOE
OE
BYTE
VIL tCE tOH VOH
DATA(Q0-Q7)
VOL
HIGH Z
Data Output
HIGH Z Data Output
tACC tBHZ VOH
DATA(Q8-Q15)
VOL
HIGH Z Data Output
HIGH Z
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AC CHARACTERISTICS --- PROGRAM OPERATIONS
SYMBOL tWC tAS tAH tDS tDH tOES tCES tCS tCH tWP tWPH tBALC tBAL tSRA tCESR tVCS tRAW 27C1610-10 DESCRIPTION MIN. MAX. Write Cycle Time 100 Address Setup Time 0 Address Hold Time 50 Data Setup Time 50 Data Hold Time 0 Output Enable Setup Time 0 CE Setup Time 0 CE Setup Time 0 CE Hold Time 0 Write Pulse Width 50 Write Pulse Width High 30 Word Address Load Cycle 0.3 30 Word Address Load Time 100 Status Register Access Time 70 CE Setup before S.R. Read 70 VCC Setup Time 50 Read Operation Set Up Time After Write 20 27C1610-12 MIN. MAX. 120 0 60 60 0 0 0 0 0 60 50 0.3 30 100 90 70 50 20 UNIT ns ns ns ns ns ns ns ns ns ns ns us us ns ns us us
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Figure 3. COMMAND WRITE TIMING WAVEFORMS
CE
tOES tCS
OE
tAH tAS
ADDRESSES
VALID
tDS
tDH
DATA (Q0~Q15)
HIGH Z DIN
VCC
tVCS
10V BYTE/VPP
VIH VIL
NOTE: 1.BYTE/VPP pin should be static at 10V+0.5V during Write operation. 2.BYTE/VPP pin should be static at TTL, or CMOS level, during Read operation.
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Figure 4. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS
A0~A5
55H
AAH
55H
Word offset Address
Last Word offset Address
A6~A14
tAS
55H
tAH
2AH
55H
Page Address
A15~A19
tWC
Page Address
tBALC
tBAL
CE
tWP
tCES
OE
tRAW
10V BYTE/VPP VIH VIL VIH
tDS tDH
VIL
tSRA
DATA Q0~Q15
AAH
55H
A0H
Write Data
Last Write Data
SRD
NOTE: 1.BYTE/VPP should be static at 10V+0.5V during page programming 2.Before OE going low to "read mode", BYTE/VPP must from VH(10V) to VIH or VIL
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PROGRAMMING PERFORMANCE
PARAMETER Page Programming Time Chip Programming Time Byte Program Time MIN. LIMITS TYP. 0.9 14 7 MAX. 27 150 UNITS ms sec us
LATCHUP CHARACTERISTICS
Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. MIN. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
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PACKAGE INFORMATION 42-PIN PLASTIC DIP (600 mil)
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Revision History
Revision No. Description 1.3 Changed title from "Advanced Information" to "Preliminary" Page P1 Date APR/26/2000
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